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W28F321BB/TB 32MBIT (2MBIT x 16) PAGE MODE DUAL WORK FLASH MEMORY
1. GENERAL DESCRIPTION
The W28F321, a 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low power, high density, cost efficiency, nonvolatile read/write storage solution for a wide range of applications. The product can be operated at VDD = 2.7V to 3.6V and VPP = 1.65V to 3.6V or 11.7V to 12.3V. Its low voltage operation capability greatly extends battery life for portable applications. The W28F321 provides high performance asynchronous page mode. It allows code execution directly from Flash, thus eliminating time-consuming wait states. Furthermore, its configurative partitioning architecture allows flexible dual work operation. The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and data storage. Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.
2. FEATURES
* 32M Density with 16 Bit I/O Interface * High-Performance Reads
- 4-Word User-Programmable Area
* High Performance Program with Page Buffer
- 70/25 nS 8-Word Page Mode * Configurative 4-Plane Dual Work - Flexible Partitioning - Read operations during Block Erase or (Page Buffer) Program - Status Register for Each Partition
* Low Power Operation
- 16-Word Page Buffer - 5 S/ Word (Typ.) at 12V VPP
* Operating Temperature
- -40C to +85C
* CMOS Process (P-type silicon substrate) * Flexible Blocking Architecture
- 2.7V Read and Write Operations - VDDQ for Input/Output Power Supply Isolation - Automatic Power Savings Mode Reduces ICCR in Static Mode
* Enhanced Code + Data Storage
- Eight 4k-word Parameter Blocks - Sixty-three 32k-word Main Blocks - Top or Bottom Parameter Location
* Enhanced Data Protection Features
- 5 S Typical Erase/Program Suspends
* OTP (One Time Program) Block
- Individual Block Lock and Block Lock-Down with Zero-Latency - All blocks are locked at power-up or device reset - Absolute Protection with VPP VPPLK
- 4-Word Factory-Programmed Area
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- Block Erase, Full Chip Erase, (Page Buffer) Word Program Lockout during Power Transitions
* Automated Erase/Program Algorithms
- Basic Command Set
* Extended Cycling Capability
- Minimum 100,000 Block Erase Cycles
* Chip-Size Packaging
- 3.0V Low-Power 11 S/ Word (Typ.) Programming - 12V No Glue Logic 9 S/ Word (Typ.) Production Programming and 0.5s Erase (Typ.)
* Cross-Compatible Command Support
- 0.75 mm pitch 48-Ball TFBGA(7mm x 7mm)
* ETOXTM Flash Technology * No designed or rated as radiation hardened
* ETOX is a trademark of Intel Corporation.
- Common Flash Interface (CFI)
3. PIN CONFIGURATION
1
2
A11
3
A8
4
VPP
5
#WP
6
A19
7
A7
8
A4
A
A13
B
A14
A10
#WE
#RESET
A18
A17
A5
A2
0.75mm pitch 48-Ball TFBGA Pinout 7 x 7 mm TOP VIEW
C
A15
A12
A9
NC
A20
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
#CE
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
Vss
F
Vss
DQ7
DQ13
DQ4
V
DD
DQ10
DQ1
#OE
Figure 1. 0.75 mm pitch TFBGA 48-Ball Pinout
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Table 1. Pin Descriptions
SYMBOL A0 - A20 TYPE INPUT INPUT/ OUTPUT NAME AND FUNCTION ADDRESS INPUTS: Inputs for addresses. 32M: A0 - A20. DATA INPUT/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code, identifier code and partition configuration register code reads. Data pins float to high impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. #CE-high (VIH) deselects the device and reduces power consumption to standby levels. RESET: When low (VIL), #RESET resets internal automation and inhibits write operations, which provides data protection. #RESET-high (VIH) enables normal operation. After power-up or reset mode, the device is automatically set to read array mode. #RESET must be low during power-up/down. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of #CE or #WE (whichever goes high first). WRITE PROTECT: When #WP is VIL, locked-down blocks cannot be unlocked. Erase or program operation can be executed to the blocks which are not locked and lockeddown. When #WP is VIH, lock-down is disabled. MONITORING POWER SUPPLY VOLTAGE: VPP is not used for power supply pin. With VPP VPPLK, block erase, full chip erase, (page buffer) program or OTP program cannot be executed and should not be attempted. VPP INPUT Applying 12V0.3V to VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin. Applying 12V0.3V to VPP during erase/program can only be done for a maximum of 1,000 cycles on each block. VPP may be connected to 12V0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits may reduce block cycling capability or cause permanent damage. DEVICE POWER SUPPLY (2.7V to 3.6V): With VDD VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VDD voltage (see DC Characteristics) produce spurious results and should not be attempted. INPUT/OUTPUT POWER SUPPLY (2.7V to 3.6V): Power supply for all input/output pins. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated.
DQ0 - DQ15
#CE
INPUT
#RESET #OE #WE #WP
INPUT INPUT INPUT INPUT
VDD VDDQ VSS NC
SUPPLY SUPPLY SUPPLY
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Table 2. Simultaneous Operation Modes Allowed with Four Planes(1,2)
THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE PARTITION IS Read Array Read ID/OTP Read Status Read Query Word Program Page Buffer Program OTP Program Block Erase Full Chip Erase Program Suspend Block Erase Suspend
Notes: 1. "X" denotes the operation available. 2. Configurative Partition Dual Work Restrictions: Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition. Only one partition can be erased or programmed at a time - no command queuing. Commands must be written to an address within the block targeted by that command.
Read Array X X X X X X
Read Read Read ID/OTP Status Query X X X X X X X X X X X X X X X X X X X
Word Program X X X X
Page Buffer Program X X X X
OTP Program
Full Block Program Chip Erase Suspend Erase X X X X X X X
Block Erase Suspend X X X X X X
X
X X
X
X
X X
X
X X
X X
X X
X X X X X
X
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BLOCK NUMBER
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
ADDRESS RANGE
1FF000h - 1FFFFFh 1FE000h - 1FEFFFh 1FD000h - 1FDFFFh 1FC000h - 1FCFFFh 1FB000h - 1FBFFFh 1FA000h - 1FAFFFh 1F9000h - 1F9FFFh 1F8000h - 1F8FFFh 1F0000h - 1F7FFFh 1E8000h - 1EFFFFh 1E0000h - 1E7FFFh 1D8000h - 1DFFFFh 1D0000h - 1D7FFFh 1C8000h - 1CFFFFh 1C0000h - 1C7FFFh 1B8000h - 1BFFFFh 1B0000h - 1B7FFFh 1A8000h - 1AFFFFh 1A0000h - 1A7FFFh 198000h - 19FFFFh 190000h - 197FFFh 188000h - 18FFFFh 180000h - 187FFFh 178000h - 17FFFFh 170000h - 177FFFh 168000h - 16FFFFh 160000h - 167FFFh 158000h - 15FFFFh 150000h - 157FFFh 148000h - 14FFFFh 140000h - 147FFFh 138000h - 13FFFFh 130000h - 137FFFh 128000h - 12FFFFh 120000h - 127FFFh 118000h - 11FFFFh 110000h - 117FFFh 108000h - 10FFFFh 100000h - 107FFFh
BLOCK NUMBER ADDRESS RANGE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 0F8000h - 0FFFFFh 0F0000h - 0F7FFFh 0E8000h - 0EFFFFh 0E0000h - 0E7FFFh 0D8000h - 0DFFFFh 0D0000h - 0D7FFFh 0C8000h - 0CFFFFh 0C0000h - 0C7FFFh 0B8000h - 0BFFFFh 0B0000h - 0B7FFFh 0A8000h - 0AFFFFh 0A0000h - 0A7FFFh 098000h - 09FFFFh 090000h - 097FFFh 088000h - 08FFFFh 080000h - 087FFFh 078000h - 07FFFFh 070000h - 077FFFh 068000h - 06FFFFh 060000h - 067FFFh 058000h - 05FFFFh 050000h - 057FFFh 048000h - 04FFFFh 040000h - 047FFFh 038000h - 03FFFFh 030000h - 037FFFh 028000h - 02FFFFh 020000h - 027FFFh 018000h - 01FFFFh 010000h - 017FFFh 008000h - 00FFFFh 000000h - 007FFFh
PLANE3 (PARAMETER PLANE)
PLANE2 (UNIFORM PLANE)
Figure 2.1 Top Parameter Memory Map
PLANE0 (UNIFORM PLANE)
PLANE1 (UNIFORM PLANE)
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BLOCK NUMBER
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
ADDRESS RANGE
1F8000H - 1FFFFFH 1F0000H - 1F7FFFH 1E8000H - 1EFFFFH 1E0000H - 1E7FFFH 1D8000H - 1DFFFFH 1D0000H - 1D7FFFH 1C8000H - 1CFFFFH 1C0000H - 1C7FFFH 1B8000H - 1BFFFFH 1B0000H - 1B7FFFH 1A8000H - 1AFFFFH 1A0000H - 1A7FFFH 198000H - 19FFFFH 190000H - 197FFFH 188000H - 18FFFFH 180000H - 187FFFH 178000H - 17FFFFH 170000H - 177FFFH 168000H - 16FFFFH 160000H - 167FFFH 158000H - 15FFFFH 150000H - 157FFFH 148000H - 14FFFFH 140000H - 147FFFH 138000H - 13FFFFH 130000H - 137FFFH 128000H - 12FFFFH 120000H - 127FFFH 118000H - 11FFFFH 110000H - 117FFFH 108000H - 10FFFFH 100000H - 107FFFH
BLOCK NUMBER
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD
ADDRESS RANGE
0F8000H - 0FFFFFH 0F0000H - 0F7FFFH 0E8000H - 0EFFFFH 0E0000H - 0E7FFFH 0D8000H - 0DFFFFH 0D0000H - 0D7FFFH 0C8000H - 0CFFFFH 0C0000H - 0C7FFFH 0B8000H - 0BFFFFH 0B0000H - 0B7FFFH 0A8000H - 0AFFFFH 0A0000H - 0A7FFFH 098000H - 09FFFFH 090000H - 097FFFH 088000H - 08FFFFH 080000H - 087FFFH 078000H - 07FFFFH 070000H - 077FFFH 068000H - 06FFFFH 060000H - 067FFFH 058000H - 05FFFFH 050000H - 057FFFH 048000H - 04FFFFH 040000H - 047FFFH 038000H - 03FFFFH 030000H - 037FFFH 028000H - 02FFFFH 020000H - 027FFFH 018000H - 01FFFFH 010000H - 017FFFH 008000H - 00FFFFH 007000H - 007FFFH 006000H - 006FFFH 005000H - 005FFFH 004000H - 004FFFH 003000H - 003FFFH 002000H - 002FFFH 001000H - 001FFFH 000000H - 000FFFH
PLANE3 (UNIFORM PLANE)
PLANE2 (UNIFORM PLANE)
Figure 2.2 Bottom Parameter Memory Map
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PLANE0 (PARAMETER PLANE)
PLANE1 (UNIFORM PLANE)
W28F321BB/TB
Table 3. Identifier Codes and OTP Address for Read Operation
CODE Manufacture Code Device Code Manufacture Code Top Parameter Bottom Parameter Block is Unlocked Block Lock Configuration Code Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code OTP
Notes: 1. The address A20 - A16 are shown in below table for reading the manufacturer, device, lock configuration, device configuration code and OTP data. 2. Bottom parameter device has its parameter blocks in the plane0 (The lowest address). Top parameter device has its parameter blocks in the plane3 (The highest address). 3. DQ15 - DQ2 are reserved for future implementation. 4. PCRC = Partition Configuration Register Code. 5. OTP - LK = OTP Block Lock configuration. 6. OTP = OTP Block data.
ADDRESS [A15 - A0] (1) 0000H 0001H
DATA [DQ15 - DQ0] 00B0H 00B4H 00B5H DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 PCRC OTP-LK OTP
NOTES
2 2 3 3 3 3 4 5 6
Block Address +2
Partition Configuration register OTP Lock OTP
0006H 0080H 0081-0088H
Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1)
PARTITION CONFIGURATION REGISTER(2) PCR.10 0 0 0 1 0 1 1 1
Notes: 1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read Identifier Codes/OTP command (90H). 2. Refer to Table 12 for the partition configuration register.
PCR.9 0 0 1 0 1 1 0 1
PCR.8 0 1 0 0 1 0 1 1 00H
ADDRESS (32M-BIT DEVICE) [A20 - A16]
00H or 08H 00H or 10H 00H or 18H 00H or 08H or 10H 00H or 10H or 18H 00H or 08H or 18H 00H or 08H or 10H or 18H
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[A20-A0] 000088H
Customer Programmable Area
000085H 000084H
Factory Programmed Area
000081H 000080H
Reserved for Future Implementation (DQ15 - DQ2)
Customer programmable Area Lock Bit (DQ1) Factory programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map for OTP Program (The area outside 80H - 88H cannot be used.)
Table 5. Bus Operations (1, 2)
MODE Read Array Output Disable Standby Reset Read Identifier Codes/OTP Read Query Write
Notes: 1. Refer to DC Characteristics. When VPP VPPLK, memory contents can be read, but cannot be altered. 2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and VPPH1/2 voltages. 3. #RESET at VSS 0.2V ensures the lowest power consumption. 4. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when VPP = VPPH1/2 and VDD = 2.7V to 3.6V. Command writes involving full chip erase are reliably executed when VPP = VPPH1 and VDD = 2.7V to 3.6V. 5. Refer to Table 6 for valid DIN during a write operation. 6. Never hold #OE low and #WE low at the same timing. 7. Refer to Appendix for more information about query code.
NOTE 6
#RESET VIH VIH VIH
#CE VIL VIL VIH X VIL VIL VIL
#OE VIL VIH X X VIL VIL VIH
#WE VIH VIH X X VIH VIH VIL
ADDRESS X X X X See Table 3, 4 See Appendix X
VPP X X X X X X X
DQ0 - 15 DOUT High Z High Z High Z See Table 3, 4 See Appendix DIN
3 6 6, 7 4, 5, 6
VIL VIH VIH VIH
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Table 6. Command Definitions(11)
COMMAND Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock Bit Clear Block Lock Bit Set Block Lock-down Bit OTP Program Set Partition configuration Register
Notes: 1. Bus operations are defined in Table 5. 2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle. X = Any valid address within the device. PA = Address within the selected partition. IA = Identifier codes address (See Table 3 and Table 4). QA = Query codes address. Refer to Appendix for details. BA = Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA = Address of memory location for the Program command or the first address for the Page Buffer Program command. OA = Address of OTP block to be read or programmed (See Figure 3). PCRC = Partition configuration register code presented on the address A0 - A15. 3. ID = Data read from identifier codes. (See Table 3 and Table 4). QD = Data read from query database. Refer to Appendix for details. SRD = Data read from status register. See Table 10 and Table 11 for a description of the status register bits. WD = Data to be programmed at location WA. Data is latched on the rising edge of #WE or #CE (whichever goes high first). OD = Data to be programmed at location OA. Data is latched on the rising edge of #WE or #CE (whichever goes high first). N-1 = N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when #RESET is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address within the target partition to be programmed and the confirm command (D0H). Refer to Appendix for details.
BUS CYCLES REQ'D. 1 2 2 2 1 2 2 2 4 1 1 2 2 2 2 2
NOTE 2 2, 3, 4 2, 3, 4 2, 3 2 2, 3, 5 2, 5, 9 2, 3, 5, 6 2, 3, 5, 7 2, 8, 9 2, 8, 9 2 2, 10 2 2, 3, 9 2, 3
FIRST BUS CYCLE Oper(1) Addr(2) Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write PA PA PA PA PA BA X WA WA PA PA BA BA BA OA PCRC Data(3) FFH 90H 98H 70H 50H 20H 30H 40H or 10H E8H B0H D0H 60H 60H 60H C0H 60H
SECOND BUS CYCLE Oper(1) Addr(2) Read Read Read Write Write Write Write Data(3)
IA or OA ID or OD QA QD PA SRD BA X WA WA D0H D0H WD N-1
Write Write Write Write Write
BA BA BA OA PCRC
01H D0H 2FH OD 04H
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8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while the block erase operation is being suspended. 10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when #WP is VIL. When #WP is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. Commands other than those shown above are reserved by Winbond for future device implementations and should not be used.
Table 7. Functions of Block Lock(5) and Block Lock-Down
CURRENT STATE
State [000] [001](3) [011] [100] [101](3) [110](4) [111]
Notes:
#WP 0 0 0 1 1 1 1
DQ1(1) 0 0 1 0 0 1 1
DQ0(1) 0 1 1 0 1 0 1
State Name Unlocked Locked Locked-down Unlocked Locked Lock-down Disable Lock-down Disable
Erase/Program Allowed(2) Yes No No Yes No Yes No
1. DQ0 = 1: a block is locked; DQ0 = 0: a block is unlocked. DQ1 = 1: a block is locked-down; DQ1 = 0: a block is not locked-down. 2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (#WP = 0) or [101] (#WP = 1), regardless of the states before power-off or reset operation. 4. When #WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 5. OTP (One Time Program) block has the lock function, which is different from those described above.
Table 8. Block Locking State Transitions upon Command Write(4)
CURRENT STATE RESULT AFTER LOCK COMMAND WRITTEN (Next State)
State [000] [001] [011] [100] [101] [110] [111]
Notes:
#WP 0 0 0 1 1 1 1
DQ1 0 0 1 0 0 1 1
DQ0 0 1 1 0 1 0 1
Set Lock(1) [001] No Change(3) No Change [101] No Change [111] No Change
Clear Lock(1) No Change [000] No Change No Change [100] No Change [110]
Set Lock-down(1) [011](2) [011] No Change [111](2) [111] [111](2) No Change
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down" means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0 = 0), the corresponding block is lockeddown and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written. 4. In this state transitions table, assumes that #WP is not changed and fixed VIL or VIH.
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Table 9. Block Locking State Transitions upon #WP Transition(4) Previous State [110] Notes: 1. "#WP = 01" means that #WP is driven to VIH and "#WP = 10" means that #WP is driven to VIL. 2. State transition from the current state [011] to the next state depends on the previous state. 3. When #WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state.
(2) (2)
Current State State [000] [001] [011] [100] [101] [110] [111] #WP 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1
Result after #WP Transition (Next State) #WP = 01(1) [100] [101] [110] [111] #WP = 10(1) [000] [001] [011](3) [011]
Other than [110]
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Table 10. Status Register Definition
R 15 WSMS 7 R 14 BESS 6 R 13 BEFCES 5 R 12 PBPOPS 4 R 11 VPPS 3 R 10 PBPSS 2
NOTES:
R 9 DPS 1
R 8 R 0
SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES) 1 = Error in Block Erase or Full Chip Erase 0 = Successful Block Erase or Full Chip Erase SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM STATUS (PBPOPS) 1 = Error in (Page Buffer) Program or OTP Program 0 = Successful (Page Buffer) Program or OTP Program SR.3 = VPP STATUS (VPPS) 1 = VPP LOW Detect, Operation Abort 0 = VPP OK SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Status Register indicates the status of the partition, not WSM (Write State Machine). Even if the SR.7 is "1", the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. Check SR.7 to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.1 are invalid while SR.7 = "0". If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit, set partition configuration register attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. SR.3 is not guaranteed to report accurate feedback when VPP VPPH1, VPPH2 or VPPLK. SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status. SR.15 - SR.8 and SR.0 are reserved for future use and should be masked out when polling the status register.
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Table 11. Extended Status Register Definition
R 15 SMS 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 R 10 R 2
NOTES: After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not. XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register.
R 9 R 1
R 8 R 0
XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available
XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
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Table 12. Partition Configuration Register Definition
R 15 R 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 PC2 10 R 2 PC1 9 R 1 PC0 8 R 0
PCR.150-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2 - 0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1 - 3 are merged into one partition. (default in a bottom parameter device) 010 = Plane 0-1 and Plane2 - 3 are merged into one partition respectively. 100 = Plane 0 - 2 are merged into one partition. (default in a top parameter device) 011 = Plane 2 - 3 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 110 = Plane 0 - 1 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 101 = Plane 1 - 2 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions.
111 = There are four partitions in this configuration. Each plane corresponds to each partition respectively. Dual work operation is available between any two partitions. PCR.7 - 0 = RESERVED FOR FUTURE ENHANCEMENTS (R) NOTES: After power-up or device reset, PCR10-8 (PC2 - 0) is set to "001" in a bottom parameter device and "100" in a top parameter device. See Figure 4 for the detail on partition configuration. PCR.15 - 11 and PCR.7 - 0 are reserved for future use and should be masked out when polling the partition configuration register.
PC2 PC1 PC0
PARTITIONING FOR DUAL WORK
PARTITION0 PLANE2 PLANE3 PLANE1 PLANE0
PC2 PC1 PC0
PARTITIONING FOR DUAL WORK
PARTITION2 PLANE3 PLANE2 PARTITION1 PARTITION0 PLANE1 PLANE0 PARTITION0 PLANE1 PLANE0 PARTITION0 PLANE0 PLANE0
0
0
0
0
1
1
PARTITION1 PLANE3 PLANE2 PLANE1
PARTITION0 PLANE0
PARTITION2 PARTITION1
0
0
1
1
1
0
PARTITION1 PLANE2 PLANE3
PARTITION0 PLANE1 PLANE0
PARTITION2 PLANE3
PLANE3
PLANE2
PLANE2
PARTITION1 PLANE1 PLANE1
0
1
0
1
0
1
PARTITION1 PLANE3 PLANE2
PARTITION0 PLANE1 PLANE0
PARTITION3 PARTITION2 PARTITION1 PARTITION0
1
0
0
1
1
1
Figure 4. Partition Configuration
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PLANE3
PLANE2
W28F321BB/TB
4. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings*
Operating Temperature During Read, Erase and Program ..................................................................................... -40C to +85C(1) Storage Temperature During under Bias .............................. .................................................................................. -40C to +85C During non Bias .............................. .................................................................................. .. -65C to +125C Voltage On Any Pin (except VDD and VPP) ......... .......................................................................................... -0.5V to VDD +0.5V(2) VDD and VDDQ Supply Voltage......................... ........................................................................ -0.2V to +3.9V(2) VPP Supply Voltage..................................................................................................... .... -0.2V to +12.6V(2,3,4) Output Short Circuit Current............. .............................................................................. ...................100 mA(5)
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Notes: 1. Operating temperature is for extended temperature product defined by this specification. 2. All specified voltages are with respect to VSS. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VDD and VPP pins. During transitions, this level may undershoot to -2.0V for periods <20 nS. Maximum DC voltage on input/output pins and VDD is VDD +0.5V, which, during transitions, may overshoot to VDD +2.0V for periods <20 nS. 3. Maximum DC voltage on VPP may overshoot to +13.0V for periods <20 nS. 4. VPP erase/program voltage is normally 2.7V to 3.6V. Applying 11.7V to 12.3V to VPP during erase/program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. VPP may be connected to 11.7V to 12.3V for a total of 80 hours maximum. 5. Output shorted for no more than one second. No more than one output shorted at a time.
Operating Conditions
PARAMETER Operating Temperature VDD Supply Voltage I/O Supply Voltage VPP Voltage when Used as a Logic Control VPP Supply Voltage Main Block Erase Cycling: VPP = 3.0V Parameter Block Erase Cycling: VPP = 3.0V Main Block Erase Cycling: VPP = 12V, 80 hrs. Parameter Block Erase Cycling: VPP = 12V, 80 hrs. Maximum VPP hours at 12V SYM. TA VDD VDDQ VPPH1 VPPH2 MIN. -40 2.7 2.7 1.65 11.7 100,000 100,000 1,000 1,000 80 TYP. +25 3.0 3.0 3.0 12 MAX. +85 3.6 3.6 3.6 12.3 UNIT C V V V V Cycles Cycles Cycles Cycles Hours 1 1 1 1, 2 NOTE
Notes: 1. See DC Characteristics tables for voltage range-specific specification. 2. Applying VPP = 11.7V to 12.3V during an erase or program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. A permanent connection to VPP =11.7V to 12.3V is not allowed and can cause damage to the device.
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Capacitance(1)
TA = +25 C, f = 1 MHz
PARAMETER Input Capacitance Output Capacitance
Note: Sampled, not 100% tested.
SYM. CIN COUT
TYP. 6 10
MAX. 8 12
UNIT pF pF
CONDITION VIN = 0.0V VOUT = 0.0V
AC Input/Output Test Conditions
VDDQ INPUT 0.0 VDDQ/2 TEST POINTS VDDQ/2 OUTPUT
AC test inputs are driven at VDD(min) for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends at VDD/2. Input rise and fall times (10% to 90%) < 5 nS. Worst case speed conditions are when VDD =VDD(min). Figure 5. Transient Input/Output Reference Waveform for VDD =2.7V to 3.6V
VDDQ(min)/2 1N914
R L =3.3K ohm
DEVICE UNDER TEST
C L Includes Jig Capacitance CL
OUT
Figure 6. Transient Equivalent Testing Load Circuit
Table 13. Configuration Capacitance Loading Value TEST CONFIGURATION VDD = 2.7V to 3.6V CL(PF) 50
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W28F321BB/TB
DC Characteristics
PARAMETER Input Load Current (note 1) Output Leakage Current (note1) VDD Standby Current (note 1) VDD Automatic Power Saving Current (note 1, 4) VDD Reset Power-Down Current (note 1) Average VDD Read Current Normal Mode (note1, 7) Average VDD Read Current Page Mode (note1, 7) 8 Word Read SYM. ILI ILO ICCS ICCAS ICCD TEST CONDITIONS VDD = 2.7V to 3.6V Min. -1.0 -1.0 4 4 4 15 ICCR VDD = VDD Max., #CE = VIL, #OE = VIH, f = 5 MHz 5 VPP = VPPH1 ICCW ICCE VPP = VPPH2 VPP = VPPH1 VPP = VPPH2 20 10 10 10 10 2 2 10 2 5 2 10 2 10 10 60 20 30 30 200 5 5 30 5 15 5 200 5 200 mA mA mA mA mA A A A mA A mA A A A A Typ. Max. +1.0 +1.0 20 20 20 25 UNIT A A A A A mA
VDD = VDD Max., VDDQ = VDDQ Max., VIN/VOUT = VDDQ or VSS VDD = VDD Max. #CE = #RESET = VDDQ 0.2V, #WP = VDDQ or VSS VDD = VDD Max. #CE = VSS 0.2V, #WP = VDDQ or VSS #RESET = VSS 0.2V
VDD (Page Buffer) Program Current (note 1, 5, 7) VDD Block Erase, Full Chip Erase Current (note 1, 5, 7) VDD (Page Buffer) Program or Block Erase Suspend Current (note 1, 2, 7) VPP Standby or Read Current (note 1, 6, 7) VPP (Page Buffer) Program Current (note 1, 5, 6, 7) VPP Block Erase, Full Chip Erase Current (note 1, 5, 6, 7) VPP (Page Buffer) Program Suspend Current (note 1, 6, 7)
ICCWS #CE = VIH ICCES IPPS IPPR IPPW IPPE IPPWS VPP VDD VPP = VPPH1 VPP = VPPH2 VPP = VPPH1 VPP = VPPH2 VPP = VPPH1 VPP = VPPH2
VPP = VPPH1 VPP Block Erase Suspend Current IPPES (note 1, 6, 7) VPP = VPPH2
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DC Characteristics (continued)
PARAMETER Input Low Voltage (note 5) Input High Voltage (note 5) Output Low Voltage (note 5) Output High Voltage (note 5) VPP Lockout during Normal Operations (note 3, 5, 6) VPP during Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program Operations (note 6) VPP during Block Erase, (Page Buffer) Program or OTP Program Operations (note 6) VDD Lockout Voltage
Notes:
SYM. VIL VIH VOL VOH VPPLK VPPH1
TEST CONDITIONS
VDD = 2.7V - 3.6V Min. -0.4 VDDQ -0.4 Typ. Max. 0.4 VDDQ +0.4 0.2 VDDQ -0.2 0.4 1.65 3.0 3.6
UNIT V V V V V V
VDD = VDD Min., VDDQ = VDDQ Min., IOL = 100 A VDD = VDD Min., VDDQ = VDDQ Min., IOH = -100 A
VPPH2 VLKO
11.7 1.5
12
12.3
V V
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VDD = 3.0V and TA = +25 C unless VDD is specified. 2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW , respectively. 3. Block erases, full chip erase, (page buffer) program and OTP program are inhibited when VPP VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.) and above VPPH2 (max.). 4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when address are changed. 5. Sampled, not 100% tested. 6. VPP is not used for power supply pin. With VPP VPPLK, block erase, full chip erase, (page buffer) program and OTP program cannot be executed and should not be attempted. Applying 12V0.3V to V VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and layout considerations given to the VDD power bus. Applying 12V0.3V to VPP during erase/program can only be done for a maximum of 1,000 cycles on each block. VPP may be connected to 12V0.3V for a total of 80 hours maximum. 7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
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W28F321BB/TB
AC Characteristics - Read-only Operations(1)
VDD = 2.7V to 3.6V, TA = -40C to +85C
PARAMETER Read Cycle Time Address to Output Delay #CE to Output Delay (note 3) Page Address Access Time #OE to Output Delay (note 3) #RESET High to Output Delay #CE or #OE to Output in High Z, whichever Occurs First (note 2) #CE to Output in Low Z (note 2) #OE to Output in Low Z (note 2) Output Hold from first Occurring Address, #CE or #OE Change (note 2)
Notes:
SYM. tAVAV tAVQV tELQV TAPA tGLQV TPHQV tEHQZ, tGHQZ, TELQX tGLQX tOH
MIN. 70
MAX. 70 70 25 20 150 20
UNIT nS nS nS nS nS nS nS nS nS nS
0 0 0
1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate. 2. Sampled, not 100% tested. 3. #OE may be delayed up to tELQV to tGLQV after the falling edge of #CE without impact to tELQV.
A20-0(A)
VIH VIL
t AVQV
Valid Address
tEHQZ tGHQZ
VIH #CE(E) VIL
t ELQV
#OE(G)
VIH VIL VIH VIL
t ELQX tGLQX
#WE(W)
t GLQV
t OH
V OH DQ15-0 (D/Q) VOL V IH V IL
HIGH Z
t PHQV
Valid Output
#RESET(P)
Figure 7. AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier codes, OTP Block or Query Code
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A20-3(A)
VIH VIL
t AVQV
Valid Address
A2-0(A)
VIH VIL VIH
Valid Address
Valid Address
Valid Address
Valid Address
#CE(E)
VIL
t ELQV
t EHQZ t GHQZ
#OE(G)
VIH VIL VIH VIL V OH VOL
t PHQV t ELQX tGLQX
#WE(W)
t GLQV tAPA
t OH
DQ15-0 (D/Q)
HIGH Z
Valid Address
Valid Address
Valid Address
Valid Address
#RESET(P)
VIH VIL
Figure 8. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks
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W28F321BB/TB
AC Characteristics - Write Operations(1,2)
VDD = 2.7V to 3.6V, TA = -40C to +85C
PARAMETER Write Cycle Time #RESET High Recovery to #WE(#CE) Going Low (note 3) #CE(#WE) Setup to #WE(#CE) Going Low (note 4) #WE(#CE) Pulse Width (note 4) Data Setup to #WE(#CE) Going High (note 8) Address Setup to #WE(#CE) Going High (note 8) #CE(#WE) Hold from #WE(#CE) High Data Hold from #WE(#CE) High Address Hold from #WE(#CE) High #WE(#CE) Pulse Width High (note 5) #WP High Setup to #WE(#CE) Going High (note 3) VPP Setup to #WE(#CE) Going High (note 3) Write Recovery before Read #WP High Hold from Valid SRD (note 3, 6) VPP Hold from Valid SRD (note 3, 6) #WE(#CE) High to SR.7 Going "0" (note 3, 7)
Notes:
SYM. tAVAV tPHWL(tPHEL) tELWL(tWLEL) tWLWH(tELEH) tDVWH(tDVEH) tAVWH(tAVEH) tWHEH(tEHWH) tWHDX(tEHDX) tWHAX(tEHAX) tWHWL(tEHEL) tSHWH(tSHEH) tVVWH(tVVEH) tWHGL(tEHGL) tQVSL tQVVL tWHR0(tEHR0)
MIN. 70 150 0 60 40 50 0 0 0 30 0 200 30 0 0
MAX.
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
tAVQV+40
nS
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. A write operation can be initiated and terminated with either #CE or #WE. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from the falling edge of #CE or #WE (whichever goes low last) to the rising edge of #CE or #WE (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. 5. Write pulse width high (tWPH) is defined from the rising edge of #CE or #WE (whichever goes high first) to the falling edge of #CE or #WE (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 6. VPP should be held at VPP = VPPH1/2 until determination of block erase, (page buffer) program or OTP program success (SR.1/3/4/5 = 0) and held at VPP = VPPH1 until determination of full chip erase success (SR.1/3/5 = 0). 7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns. 8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit configuration.
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A21-0(A)
V IH V IL V IH V IL V IH V IL
Note 1
Note 2
Valid Address t AVAV
Note 3
Valid Address t AVWH (t AVEH )
Note 4
Valid Address t WHAX (t EHAX )
Note 5
#CE(E)
Note 5,6
t ELWL (t WLEL) t WHEH (t EHWH ) t WHGL (t EHGL )
Note 5,6
#OE(G)
t PHWL (t PHEL)
t WHWL (t EHEL)
#WE(W)
V IH V IL
t WLWH (t ELEH) t DVWH (t DVEH ) t WHDX (t EHDX ) D IN D IN t WHR0 (t EHR0) t WHQV1,2,3 (t EHQV1,2,3) Valid
SRD
DQ15-0(D/Q)
V IH V IL
("1")
SR.7(R) #RESET(P)
("0")
V IH V IL V IH V IL
t VVWH(t VVEH) t QVVL t SHWH(t SHEH) t QVSL
#WP(S)
VPPH1,2 VPP (V) V PPLK V IL
Figure 9. AC Waveform for Write Operations Notes: 1. VDD power-up and standby. 2. Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operation, #OE and #CE must be driven active, and #WE de-asserted.
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W28F321BB/TB
Reset Operations
t PHQV
#RESET(P)
VIH VIL VOH VOL High Z (A)Reset During Read Array Mode SR.7="1" Abort Complete
t PLPH
DQ15-0(D/Q)
Valid Output
t PLRH
t PHQV
#RESET(P)
VIH VIL VOH VOL VDD (min) High Z (B)Reset During Erase or Program Mode
t PLPH
DQ15-0(D/Q)
Valid Output
VDD
Vss
t 2VPH
t VHQV t PHQV
#RESET(P)
VIH V IL
DQ15-0(D/Q)
VOH VOL
High Z (C)#RESET Rising Timing
Valid Output
Figure 10. AC Waveform for Reset Operation
Reset AC Specifications
VDD = 2.7V to 3.6V, TA = -40C to +85C PARAMETER #RESET Low to Reset during Read (#RESET should be low during power-up.) (note 1, 2, 3) #RESET Low to Reset during Erase or Program (note 1, 3, 4) VDD 2.7V to #RESET High (note 1, 3, 5) VDD 2.7V to Output Delay (note 3)
Notes: 1. A reset time, tPHQV, is required from the later of SR.7 going "1"(High Z) or #RESET going high until outputs are valid. Refer to AC Characteristics - Read-Only Operations for tPHQV. 2. tPLPH is <100ns the device may still reset but this is not guaranteed. 3. Sampled, not 100% tested.
SYM.
MIN. 100
MAX.
UNIT nS
tPLPH tPLRH t2VPH tVHQV
22 100 1
S nS mS
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W28F321BB/TB
4. If #RESET asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing, the reset will complete within 100ns. 5. When the device power-up, holding #RESET low minimum 100ns is required after VDD has been in predefined range and also has been in stable there.
Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(3)
VDD = 2.7V to 3.6V, TA = -40C to +85C
PARAMETER
SYM.
PAGE BUFFER VPP = VPPH1 VPP = VPPH2 COMMAND IS (IN SYSTEM) (IN MANUFACTURING) UNIT USED OR NOT (1) (2) MIN. TYP.(1) MAX.(2) MIN. TYP. MAX. USED Not Used Used Not Used Used Not Used Used Not Used 0.05 0.03 0.38 0.24 11 7 36 0.3 0.6 40 0.3 0.12 2.4 1.0 200 100 400 4 5 350 10 20 5 5 10 20 0.04 0.02 0.31 0.17 9 5 27 0.2 0.5 0.12 0.06 1.0 0.5 185 90 185 4 5 S S S S S S S S S S S S
4K-Word Parameter Block Program Time (note 2) 32K-Word Main Block Program Time (note 2) Word Program Time (note 2) OTP Program Time (note 2) 4K-Word Parameter Block Erase Time (note 2) 32K-Word Main Block Erase Time (note 2) Full Chip Erase Time (note 2) (Page Buffer) Program Suspend Latency Time to Read (note 4)
tWPB tWMB tWHQV1/ tEHQV1 tWHOV1/ tEHOV1 tWHQV2/ tEHQV2 tWHQV3/ tEHQV3 tWHRH1/ tEHRH1
-
5 5
Block Erase Suspend Latency tWHRH2/ Time to Read (note 4) tEHRH2 Latency Time from Block Erase Resume Command to Block Erase Suspend Command (note 5)
Notes:
tERES
-
500
500
S
1. Typical values measured at VDD = 3.0V, VPP = 3.0V or 12V, and TA=+25C. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. 4. A latency time is required from writing suspend command (#WE or #CE going high) until SR.7 going "1". 5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished.
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W28F321BB/TB
5. ADDITIONAL INFORMATION
Recommended Operating Conditions
At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VDD #RESET (p) Vpp
*1
VDD (min) Vss VIH V IL
tVR t 2VPH t PHQV
(V) V PPH1/2 Vss VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL
tR or tF
tAVQV
tR or tF
ADDRESS (A)
Valid Address
tF t ELQV tR
#CE
(E)
#WE (W)
tF
t GLQV
tR
#OE
(G)
#WP
(S)
DATA (D/Q)
HIGH Z
Valid Output
*1 To prevent the unwanted writes, system designers should consider the design, which applies VPP to 0V during read operations and VPPH1/2 during write or erase operations.
Figure A-1. AC Timing at Device Power-up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.
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Rise and Fall Time PARAMETER VDD Rise Time (note 1) Input Signal Rise Time (note1, 2) Input Signal Fall Time (note1, 2)
Notes: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations.
SYMBOL tVR tR tF
MIN. 0.5
MAX. 30000 1 1
UNIT S/ V S/ V S/ V
Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Singal VIH(Min.)
Input Singal VIH(Min.)
VIL (Max.) Input Singal
VIL (Max.) Input Singal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.).
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W28F321BB/TB
6. ORDERING INFORMATION
PART NO. W28F321BB70L W28F321TB70L
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
ACCESS TIME (nS) 70 70
OPERATING TEMPERATURE (C) -40 C to 85 C -40 C to 85 C
BOOT BLOCK Bottom Boot Top Boot
PACKAGE 48-Ball TFBGA 48-Ball TFBGA
7. PACKAGE DIMENSION
48-Ball TFBGA (7mm x 7mm) (measurements in millimeters)
b 1 H G F E D C B A 2 3 4 5 6
CONTROL DIMENSIONS ARE IN MILLIMETERS SYMBOL 0.20 6.80 MILLIMETER MIN. NOM. MAX. e D2 D A A1 D D2 e E E2 E E2 y 0.25 7.00 1.05 INCH MIN. NOM. MAX. 0.042
0.30 0.008 0.010 0.012 7.20 0.272 0.280 0.288 0.150 BASIC
3.75 BASIC 6.80 7.00
7.20 0.272 0.280 0.288 0.210 0.004 BASIC
5.25 BASIC 0.10 BASIC 0.37 0.40
A SEATING PLANE A1
b e
0.43 0.015 0.016 0.017 0.030 BASIC
0.75 BASIC
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Publication Release Date: February 17, 2003 Revision A2
W28F321BB/TB
8. VERSION HISTORY
VERSION A1 A2 DATE Jan. 3, 2003 Feb. 17, 2003 PAGE 27 Initial Issued Modify the package dimension drawing DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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